The invention relates to an ESD protection structure having a reduced triggering voltage or reduced breakdown voltage.
A common ESD protection solution is a snap back NMOS ESD protection clamp. Conventional snap back clamps make use of the snap back triggering characteristics of the parasitic bipolar structure to switch from some critical level of drain-source breakdown into high-conductivity due to avalanche injection.
A typical CMOS device is illustrated in FIG. 1 in which the polygate can be used as a self-aligned mask to produce a small drain-source spacing between the drain 14 and the source 16. The gate which is of the order of 0.18 xcexcm in the case of 0.18 xcexcm technology allows a drain-source spacing of the order of 0.1 xcexcm to be achieved. A schematic representation of the structure of FIG. 1 is shown in FIG. 2 which defines the gap 12 in the p-well 18. The gap 12 extends between a lightly doped drain region 20 of the drain 14, and a lightly doped source region 22 of the source 16. As is shown in the electric field versus x-dimension graph in FIG. 2B, the electric field gradually increases from the source to the drain. Furthermore, the curves 24 become ever steeper as the voltage across the drain and source is increased. The effect of this is that hole concentration at the drain gradually increases with increasing electric field as shown in FIG. 2C. At the same time, the electron concentration at the source gradually increases. The breakdown voltage avalanche effect causes the holes to be swept across from the drain to the source and causes electron injection from the source to the drain. As can be seen in FIG. 2A, some of the holes are diverted into the gate 10 which is separated from the p-well only by a thin gate oxide 30. The gate coupling effect can be adjusted by adjusting the voltage on the gate thereby allowing the triggering voltage to be further reduced by limiting the number of holes that are diverted into the gate. The snap back triggering characteristic of the NMOS device of FIGS. 1 and 2, is used to switch the device into a high conductivity state with avalanche injection at some critical level of drain-source breakdown.
Unfortunately, due to parasitics in the circuit, especially PCB capacitance, triggering voltages are generally quite high, thus generating stress in the circuit due to the high currents that have to be handled by the circuit. A typical 0.18 xcexcm, 3.3 V NMOS device will display triggering voltages of about 10V. As mentioned above, in the past the dynamic triggering voltage has been reduced by adjusting the voltage on the gate. However, this only approach only allows a triggering voltage reduction of about 20%.
The breakdown characteristics of the NMOS device described above are illustrated in FIG. 3 in which the drain current versus drain-source voltage characteristics are shown. As the drain-source voltage (Vds) increases, drain current (Id) remains substantially unchanged until the breakdown voltage (Vbr) 32 is reached. This causes rapid increase in Id. Eventually the hole concentration and electron concentration at the drain and source, respectively, is reversed, as defined by the triggering voltage (Vtr) 34. At this point, even with reduced Vds, the drain current continues to increase thus defining the snap back effect.
One of the challenges in designing a snap back NMOS clamp is achieving the requisite current handling capabilities. This can be solved through the use of dual gate oxide (DGO) NMOS devices. However this is achieved at the expense of even higher triggering voltages. The need to reduce the triggering voltage is based on the maximum allowable voltage that can be handled by the protected circuit during an electrostatic discharge, heat dissipation, hot carrier degradation, and gate oxide damage. Thus there is a need to reduce the triggering voltage of NMOS snap back clamps to enhance ESD protection clamp robustness.
Another common approach to the ESD problem is the use of LVTSCRs. These typically display even higher breakdown voltages than NMOS devices. Thus, it would be desirable to be able to reduce breakdown voltage levels in these devices as well, when used as ESD protection clamps.
Referring to the typical NMOS device shown in FIG. 1, the snap back triggering voltage of NMOS is determined by the drain-source breakdown voltage, which corresponds approximately to the breakdown voltage of the junction between the N+ drain 14 and the p-well 18. For purposes of ESD protection, a dual gate oxide (DGO) NMOS is commonly used. For a given process, the breakdown voltage is a fixed value that is usually higher than the breakdown voltage of minimum dimension single gate oxide devices that are to be protected by the clamp.
According to the invention, there is provided a snap back DGO NMOS ESD protection clamp comprising a NMOS structure having an internal zener diode structure having a breakdown voltage that is lower than the breakdown voltage of the drain-p-well junction of the NMOS structure.
Further, according to the invention it is provided a method of reducing the triggering voltage of a NMOS snap back clamp comprising forming a p-n junction to define a zener diode in the NMOS structure, having a breakdown voltage that is lower than the drain-p-well junction of the NMOS structure. Preferably the p-n junction is formed near the source-p-well junction, so that at least some of the holes generated due to avalanche breakdown of the zener diode drift towards the source to reduce the potential and cause electrons to be injected from the source-p-well junction. The injected electrons may further increase the carrier multiplication rate by drifting to the drain-p-well junction. Thus, by increasing the current density, snap back is reached sooner, to provide lower triggering and breakdown voltages.
The invention is however not limited to NMOS structures. More generally, according to the invention there is provided a method of reducing the breakdown voltage of an ESD protection device, comprising forming a zener diode in the ESD device, wherein the zener diode has a lower breakdown voltage than that of the ESD device. The ESD device can be a PMOS device or a LVTSCR structure. In the case of the LVTSCR, the zener diode is formed inside or adjacent to the floating drain of the LVTSCR.
Preferably, the region formed to define the zener diode, for instance, in the case of an NMOS device, a p+ region, is formed sufficiently closely to the source of the NMOS structure to inject electrons into the source junction during zener breakdown.
Still further, according to the invention, there is provided an ESD protection device, comprising at least one highly doped region adjacent or within a drain, floating drain or drain ballast region of the ESD protection device, having the opposite polarity to said drain, floating drain or drain ballast region, to form at least one p-n junction having a lower breakdown voltage than the breakdown voltage between said drain, floating drain, or drain ballast, and the substrate or well in which the drain, floating drain, or ballast is formed.
The highly doped region may be a single region extending substantially the entire length of the drain, floating drain, or drain ballast region, or can take the form of a plurality of islands in the drain, floating drain, or drain ballast region. In the case where the highly doped region takes the form of islands, these may extend all the way through the drain, floating drain, or drain ballast region. On the other hand, where the highly doped region extends substantially along the entire length of the drain, floating drain, or drain ballast region, it is typically formed above or below the drain or drain ballast region of the device so as not to interfere with the movement of charge carriers.